1. Kazoumi Hatayama
Kazoumi Hatayama is now a research professor in Graduate School of Information Science at Nara Institute of Science and Technology (NAIST). He is engaged in research and development of design automation technologies for testing in Hitachi, Renesas and Semiconductor Technology Academic Research Center (STARC). He received his B.S., M.S. and Ph.D. degrees in applied mathematics and physics from Kyoto University, Kyoto, Japan.
Since 2008, he is serving as Asia Pacific Regional Chair of Test Technology Technical Council.
He is also serving as General Chair of 2012 Asian Test Symposium (ATS),
Special Session Co-Chair of VLSI Test Symposium (VTS) and a Program Committee member of several other conferences. He is a senior member of IEEE and the Institute of Electronics, Information and Communication Engineers (IEICE, Japan) and a member of some other societies in Japan. His research interests include DFT, BIST, ATPG, fault diagnosis and dependable system.
2. Rohit Kapur
Rohit Kapur is a scientist at Synopsys, where he works on delivering next-generation test automation solutions and manages an R&D team in Bangalore. The technologies Kapur has invented include Adaptive Scan, DFTMAX, and a solution for small delay defect testing. Kapur received a PhD in computer engineering from the University of Texas at Austin. He is an IEEE Fellow and an active member of the test community. He has chaired the test technology standards group in IEEE TTTC since 2004, has served as a member of the IEEE Computer Society's Board of Governors, and has participated as a member of the program committees of most of the conferences in IC testing, including ITC and VTS. Kapur chaired the IEEE 1450.6 standard activity and is the author a book entitled “CTL for test information for digital ICs”. He is also editor of IEEE Computing Practices publication
3. Cecilia Metra
Cecilia Metra is an Associate Professor in Electronics in the Department of Electronic, Computer Science and Systems (DEIS) of the Univ. of Bologna. In 2010 she qualified as Full Professor in electronics. She is also affiliated with the Advanced Research Center on Electronic Systems for Information and Communication Technologies E. De Castro (ARCES) of the Univ. of Bologna. She has been a Visiting Scholar at the Univ. of Washington, Seattle (USA) from 1998 to 2001, and Visiting Faculty Consultant for Intel Corporation, Santa Clara (CA) in 2002. She is the General Chair of the IEEE VLSI Test Symp. 2012, and she has been General Chair/Co-Chair of the IEEE VLSI Test Symp. 2011, IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems 2005 and 1999, the IEEE On-Line Testing Symp. 2006 and 2001, and Program Chair/Co-Chair of VTS 2009 and 2008, the IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS) 2008, The IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems 1998, the IEEE Int’l On-Line Testing Symp. 2005, 2004, 2003, and 2002. Her research interests are in the field of Design and Test of Integrated Digital Systems, Reliable and Error Resilient Systems, Fault Tolerance, On-Line Testing, Fault Modeling, Diagnosis and Debug, Emergent Technologies, Energy Harvesting and Security. She is Associate Editor in Chief of the IEEE Transactions on Computers, and Member of the Editorial Board of the Journal of Electronic Testing: Theory and Applications and the International Journal of Highly Reliable Electronic System Design She is a Senior Member and a Golden Core member of the IEEE Computer Society. |
